XC4013-6PQ240C Xilinx Inc, XC4013-6PQ240C Datasheet - Page 18

• Manufacturer Part Number: XC4013-6PQ240C
• Description: IC LOGIC CL ARRAY 13K GAT 240PQ
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4013-6PQ240C

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 192
• Number Of Gates: 13000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1074

XC4000, XC4000A, XC4000H Logic Cell Array Families
Figure 18. TBUFs Driving Horizontal Longlines.
Interconnects
The XC4000 families use a hierarchy of interconnect
resources.
•
•
•
Each CLB column has four dedicated Vertical Longlines,
each of these lines has access to a particular Primary
Global Net, or to any one of the Secondary Global Nets.
The Global Nets avoid clock skew and potential hold-time
General purpose single-length and double-length
lines offer fast routing between adjacent blocks, and
highest flexibility for complex routes, but they incur a
delay every time they pass through a switch matrix.
Longlines run the width or height of the chip with
negligible delay variations. They are used for signal
distribution over long distances. Some Horizontal
Longlines can be driven by 3-state or open-drain
drivers, and can thus implement bidirectional buses
or wired-AND decoding.
Global Nets are optimized for the distribution of clock
and time-critical or high-fan-out control signal. Four
pad-driven Primary Global Nets offer shortest delay
and negligible skew. Four pad-driven Secondary
Global Nets have slightly longer delay and more
skew due to heavier loading.
3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
“KEEPER”
~100 k
+5 V
Open Drain Buffers Implement a Wired-AND Function. When all the buffer
~5 k
D
A
inputs are High the pull-up resistor(s) provide the High output.
D
A
A
D
Z
B
=
Z
Active High T is Identical to
D
Active Low Output Enable.
=
A
D
•
T
D
D
A
B
B
B
•
• ( D
A
+
C
D
D
D
2-24
+ D
B
C
D
•
D
B
OE
)
Figure 17. XC4000 Global Net Distribution. Four Lines per
problems. The user must specify these Global Nets for all
timing-sensitive global signal distribution.
• (
+ D
D
E
C
+
•
D
D
C
C
C
F
+
)
…
… +
Column; Eight Inputs in the Four Chip Corners.
D
N
D
D
•
E
F
N
D
N
N
~5 k
+5 V
SECONDARY
GLOBAL NETS
PRIMARY
GLOBAL NETS
X1007
X1027
X1006