EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 202
EP4CE55F29C8LN
Manufacturer Part Number
EP4CE55F29C8LN
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29C8LN
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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8–36
Table 8–10. PS Configuration Timing Parameters For Cyclone IV Devices (Part 2 of 2)
Cyclone IV Device Handbook, Volume 1
Notes to
(1) This information is preliminary.
(2) Applicable for Cyclone IV GX and Cyclone IV E devices with 1.2-V core voltage.
(3) Applicable for Cyclone IV E devices with 1.0-V core voltage.
(4) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(5) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(6) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
(7) Cyclone IV E devices with 1.0-V core voltage have slower F
t
t
t
t
t
t
t
t
t
t
t
f
CF2ST1
CF2CK
ST2CK
DH
CD2UM
CD2CU
CD2UMC
DSU
CH
CL
CLK
MAX
Symbol
Table
8–10:
nCONFIG high to
nSTATUS high
nCONFIG high to first
rising edge on DCLK
nSTATUS high to first
rising edge of DCLK
Data hold time after
rising edge on DCLK
CONF_DONE high to
user mode
CONF_DONE high to
CLKUSR enabled
CONF_DONE high to
user mode with
CLKUSR option on
Data setup time before
rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
DCLK frequency
Parameter
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera USB-Blaster
USB port download cable, MasterBlaster™ serial and USB communications cable,
ByteBlaster II parallel port download cable, the ByteBlasterMV
download cable, and the EthernetBlaster communications cable.
In the PS configuration with a download cable, an intelligent host (such as a PC)
transfers data from a storage device to the Cyclone IV device through the download
cable.
(6)
(7)
Cyclone IV
t
CD2CU
4 × maximum DCLK period
3.2
3.2
7.5
+ (3,192 × CLKUSR period)
—
5
MAX
(2)
Minimum
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
230
when compared with Cyclone IV GX devices with 1.2-V core voltage.
300
—
2
0
(4)
Cyclone IV E
6.4
6.4
15
—
8
(3)
Cyclone IV
133
—
—
—
—
(Note 1)
© December 2010 Altera Corporation
(2)
Maximum
230
650
—
—
—
—
—
™
Cyclone IV E
(5)
parallel port
—
—
—
—
66
(3)
Configuration
MHz
Unit
µs
µs
µs
µs
—
—
ns
ns
ns
ns
ns
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