EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 309

• Manufacturer Part Number: EP4CE55F29C8LN
• Description: IC CYCLONE IV FPGA 55K 780FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F29C8LN

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 374
• Voltage - Supply: 0.97 V ~ 1.03 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
Table 1–9. High- and Low-Speed Clock Sources for Each Channel in Non-Bonded Channel Configuration
© December 2010 Altera Corporation
F324 and smaller
F484 and larger
Note to
(1) MPLL_7 and GXBL1 are not applicable for transceivers in F484 package
Package
Table 1–9
:
Transceiver Block
Table 1–9
Figure 1–31
transceivers in F324 and smaller packages, and in F484 and larger packages in
non-bonded channel configuration.
Figure 1–31. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F324 and
Smaller Packages
Notes to
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
GXBL1
GXBL0
GXBL0
Figure 1–31
(1)
lists the high- and low-speed clock sources for each channel.
and
:
Figure 1–32
Transceiver Channel
Channels 0, 1
Channels 2, 3
Channels 0, 1
Channels 2, 3
All channels
Transceiver
show the high- and low-speed clock distribution for
GXBL0
Block
Ch3
Ch2
Ch1
Ch0
(1)
(1)
MPLL_2
MPLL_1
TX PMA
TX PMA
TX PMA
TX PMA
MPLL_5/GPLL_1
MPLL_7/MPLL_6
High- and Low-Speed Clocks Sources
MPLL_1
MPLL_5
MPLL_7
Option 1
(3)
(2)
Cyclone IV Device Handbook, Volume 2
MPLL_6/MPLL_7
MPLL_8/GPLL_2
MPLL_2
MPLL_6
MPLL_8
Option 2
(1)
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