EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 42
EP4CE55F29C8LN
Manufacturer Part Number
EP4CE55F29C8LN
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29C8LN
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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3–6
Mixed-Width Support
Asynchronous Clear
Cyclone IV Device Handbook, Volume 1
1
Figure 3–4. Cyclone IV Devices Address Clock Enable During Write Cycle Waveform
M9K memory blocks support mixed data widths. When using simple dual-port, true
dual-port, or FIFO modes, mixed width support allows you to read and write
different data widths to an M9K memory block. For more information about the
different widths supported per memory mode, refer to
page
Cyclone IV devices support asynchronous clears for read address registers, output
registers, and output latches only. Input registers other than read address registers are
not supported. When applied to output registers, the asynchronous clear signal clears
the output registers and the effects are immediately seen. If your RAM does not use
output registers, you can still clear the RAM outputs using the output latch
asynchronous clear feature.
Asserting asynchronous clear to the read address register during a read operation
may corrupt the memory content.
Figure 3–5
Figure 3–5. Output Latch Asynchronous Clear Waveform
aclr at latch
latched address
(inside memory)
3–7.
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
wraddress
aclr
clk
shows the functional waveform for the asynchronous clear feature.
q
inclock
wren
data
an
XX
a0
00
a1
XX
a0
01
a1
a2
XX
01
02
a2
XX
XX
XX
a1
02
Chapter 3: Memory Blocks in Cyclone IV Devices
a3
03
00
“Memory Modes” on
© November 2009 Altera Corporation
04
a4
a0
a4
03
a5
05
a1
04
a5
05
a6
06
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