EP4CE55F29C8LN Altera, EP4CE55F29C8LN Datasheet - Page 45
EP4CE55F29C8LN
Manufacturer Part Number
EP4CE55F29C8LN
Description
IC CYCLONE IV FPGA 55K 780FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F29C8LN
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
374
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Simple Dual-Port Mode
Table 3–3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
© November 2009 Altera Corporation
8192 × 1
4096 × 2
2048 × 4
1024 × 8
512 × 16
256 × 32
1024 × 9
512 × 18
256 × 36
Read Port
8192
v
v
v
v
v
v
—
—
—
× 1
Simple dual-port mode supports simultaneous read and write operations to different
locations.
Figure 3–8. Cyclone IV Devices Simple Dual-Port Memory
Note to
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone IV devices M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
configurations.
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “Don’t
Care” data at that location or output “Old Data”. To choose the desired behavior, set
the Read-During-Write option to either Don’t Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to
4096
v
v
v
v
v
v
—
—
—
Figure
× 2
Figure 3–8
3–8:
2048
v
v
v
v
v
v
—
—
—
× 4
shows the simple dual-port memory configuration.
“Read-During-Write Operations” on page
1024
v
v
v
v
v
v
—
—
—
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
× 8
Write Port
512
v
v
v
v
v
v
—
—
—
× 16
256
rd_addressstall
Table 3–3
v
v
v
v
v
v
—
—
—
rdaddress[ ]
× 32
rdclocken
rdclock
(Note 1)
rden
q[ ]
1024
lists mixed-width
Cyclone IV Device Handbook, Volume 1
—
—
—
—
—
—
v
v
v
× 9
3–15.
512
—
—
—
—
—
—
v
v
v
× 18
256
v
v
v
—
—
—
—
—
—
× 36
3–9
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