EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 207

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
The DCLK speed must be below the specified system frequency to ensure correct
configuration. No maximum DCLK period exists, which means you can pause
configuration by halting DCLK for an indefinite amount of time.
The external host device can also monitor the CONF_DONE and INIT_DONE pins to
ensure successful configuration. The CONF_DONE pin must be monitored by the
external device to detect errors and to determine when programming is complete. If
all configuration data is sent, but CONF_DONE or INIT_DONE has not gone high, the
external device must reconfigure the target device.
Figure 8–20
circuit is similar to the FPP configuration circuit for a single device, except the
Cyclone IV devices are cascaded for multi-device configuration.
Figure 8–20. Multi-Device FPP Configuration Using an External Host
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts
the second device to begin configuration. The second device in the chain begins
configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in the chain.
Configuration signals may require buffering to ensure signal integrity and prevent
clock skew problems. Ensure that the DCLK and DATA lines are buffered. All devices
initialize and enter user mode at the same time, because all device CONF_DONE pins
are tied together.
All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,
configuration stops for the entire chain and the entire chain must be reconfigured. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
(MAX II Device or
Microprocessor)
External Host
chain. V
refer to
overshoot outlined in
ADDR
Figure
Memory
CC
Table 8–4 on page 8–8
DATA[7..0]
must be high enough to meet the V
shows how to configure multiple devices with a MAX II device. This
8–20:
10 k
V
Equation 8–1 on page
CCIO
(1) V
10 k
and
CCIO
GND
Table 8–5 on page
CCIO
(1)
Buffers (5)
supply voltage of the I/O bank in which the nCE pin resides.
8–5.
IH
CONF_DONE
nSTATUS
nCE
DATA[7..0] (5)
nCONFIG
DCLK (5)
Cyclone IV Device 1
specification of the I/O on the device and the external host.
MSEL[3..0]
8–9. Connect the MSEL pins directly to V
nCEO
(4)
V
Cyclone IV Device Handbook, Volume 1
CCIO
10 k
(2)
CONF_DONE
nSTATUS
nCE
DATA[7..0] (5)
nCONFIG
DCLK (5)
Cyclone IV Device 2
MSEL[3..0]
CCA
nCEO
or GND.
N.C. (3)
8–41
(4)