EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 307

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
© December 2010 Altera Corporation
The CDR unit in each receiver channel gets the CDR clocks from one of the two
multipurpose PLLs directly adjacent to the transceiver block. The CDR clocks
distribution network is segmented by bidirectional tri-state buffers as shown in
Figure 1–29
multipurpose PLLs to drive a number of contiguous segmented paths to reach the
intended receiver channel. Interleaving the CDR clocks from the two multipurpose
PLLs is not supported.
For example, based on
channels 0, 1, and 3, while MPLL_2 driving receiver channel 2 is not supported. In this
case, only one multipurpose PLL can be used for the receiver channels.
Figure 1–29. CDR Clocking for Transceiver Channels in F324 and Smaller Packages
Note to
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
Figure 1–30. CDR Clocking for Transceiver Channels in F484 and Larger Packages
Figure
1–29:
and
Figure
Figure
1–30. This requires the CDR clocks from either one of the two
Transceiver
Transceiver
GXBL1
GXBL0
Block
Block
Transceiver
GXBL0
Block
1–29, a combination of MPLL_1 driving receiver
Ch3
Ch2
Ch1
Ch0
Ch3
Ch2
Ch1
Ch0
MPLL_8
MPLL_7
MPLL_6
MPLL_5
Ch2
Ch1
Ch0
Ch3
(1)
(1)
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
MPLL_2
MPLL_1
CDR
CDR
CDR
CDR
clocks
clocks
CDR
Not applicable in
CDR
F484 package
clocks
CDR
Cyclone IV Device Handbook, Volume 2
1–27