EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 424

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–34
Functional Simulation of the Dynamic Reconfiguration Process
Document Revision History
Table 3–8. Document Revision History
Cyclone IV Device Handbook, Volume 2
December 2010
July 2010
Date
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This section describes the points to be considered during functional simulation of the
dynamic reconfiguration process.
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Table 3–8
Version
2.0
1.0
Channel reconfiguration and PMA reconfiguration mode select - read operation
option:
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■
Enable self recovery option—when you select this option, the
ALTGX_RECONFIG MegaWizard Plug-In Manager provides the error output
port. The dynamic reconfiguration controller quits an operation if it did not
complete within the expected number of clock cycles. After recovering from the
illegal operation, the dynamic reconfiguration controller deasserts the busy signal
and asserts the error output port for two reconfig_clk cycles.
You must connect the ALTGX_RECONFIG instance to the
ALTGX_instance/ALTGX instances in your design for functional simulation.
The functional simulation uses a reduced timing model of the dynamic
reconfiguration controller. The duration of the offset cancellation process is 16
reconfig_clk clock cycles for functional simulation only.
The gxb_powerdown signal must not be asserted during the offset cancellation
sequence (for functional simulation and silicon).
The reconfig_mode_sel input port is set to 3’b001 (Channel reconfiguration
mode)
The read signal is asserted
lists the revision history for this chapter.
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Initial release.
Updated for the Quartus II software version 10.1 release.
Updated
Added
Updated
Updated
Reconfiguration”,
Controls Reconfiguration
Reconfiguration”sections.
Table
Table
Figure
“Offset Cancellation
3–7.
3–1,
3–1,
“Data Rate Reconfiguration Mode Using RX Local
Table
Figure
3–2,
Mode”, and
3–11,
Feature”,
Table
Functional Simulation of the Dynamic Reconfiguration Process
Changes Made
Figure
3–3,
“Control and Status Signals for Channel
“Error Indication During Dynamic
3–13, and
Table
Chapter 3: Cyclone IV Dynamic Reconfiguration
3–4,
Figure
© December 2010 Altera Corporation
Table
3–5, and
3–14.
Table
Divider”,
3–6.
“PMA