EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 319

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
FPGA Fabric-Transceiver Interface Clocking
Table 1–11. FPGA Fabric-Transceiver Interface Clocks
Table 1–12. Automatic TX Phase Compensation FIFO Write Clock Selection
© December 2010 Altera Corporation
tx_clkout
rx_clkout
coreclkout
fixed_clk
reconfig_clk (1),
(2)
cal_blk_clk
Notes to
(1) Offset cancellation process that is executed after power cycle requires reconfig_clk clock. The reconfig_clk must be driven with a
(2) For the supported clock frequency range, refer to the
Channel Configuration
Non-bonded
Bonded
free-running clock and not derived from the transceiver blocks.
Clock Name
Table 1–11
f
1
(2)
:
The FPGA fabric-transceiver interface clocks consists of clock signals from the FPGA
fabric to the transceiver blocks, and from the transceiver blocks to the FPGA fabric.
These clock resources use the global clock networks (GCLK) in the FPGA core.
For information about the GCLK resources in the Cyclone IV GX devices, refer to
Clock Networks and PLLs in Cyclone IV Devices
Table 1–11
In the transmitter datapath, TX phase compensation FIFO forms the FPGA
fabric-transmitter interface. Data and control signals for the transmitter are clocked
with the FIFO write clock. The FIFO write clock supports automatic clock selection by
the Quartus II software (depending on channel configuration), or user-specified clock
from tx_coreclk port.
FIFO write clock selection by the Quartus II software.
The Quartus II software assumes automatic clock selection for TX phase
compensation FIFO write clock if you do not enable the tx_coreclk port.
When using user-specified clock option, ensure that the clock feeding tx_coreclk
port has 0 PPM difference with the TX phase compensation FIFO read clock.
tx_clkout clock feeds the FIFO write clock. tx_clkout is forwarded through the transmitter
channel from low-speed clock, which also feeds the FIFO read clock.
coreclkout clock feeds the FIFO write clock for the bonded channels. coreclkout clock is
the common bonded low-speed clock, which also feeds the FIFO read clock in the bonded channels.
Transceiver dynamic reconfiguration and
125MHz receiver detect clock in PIPE
Transceiver calibration block clock
Phase compensation FIFO clock
Phase compensation FIFO clock
Phase compensation FIFO clock
lists the FPGA fabric-transceiver interface clocks.
offset cancellation clock
Clock Description
mode
Cyclone IV Device Data
Table 1–12
Quartus II Selection
details the automatic TX phase compensation
Sheet.
chapter.
Transceiver to FPGA fabric
Transceiver to FPGA fabric
Transceiver to FPGA fabric
FPGA fabric to transceiver
FPGA fabric to transceiver
FPGA fabric to transceiver
Interface Direction
Cyclone IV Device Handbook, Volume 2
1–39