EP4CE55F23C7 Altera, EP4CE55F23C7 Datasheet - Page 347

• Manufacturer Part Number: EP4CE55F23C7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23C7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
© December 2010 Altera Corporation
1
Clock Rate Compensation
In XAUI mode, the rate match FIFO compensates up to ±100 PPM (200 PPM total)
difference between the upstream transmitter and the local receiver reference clock.
The XAUI protocol requires the transmitter to send /R/ (/K28.0/) code groups
simultaneously on all four lanes (denoted as ||R|| column) during inter-packet
gaps, adhering to rules listed in the IEEE P802.3ae specification.
The rate match operation begins after rx_syncstatus and rx_channelaligned
are asserted. The rx_syncstatus signal is from the word aligner, indicating that
synchronization is acquired on all four channels, while rx_channelaligned signal
is from the deskew FIFO, indicating channel alignment.
The rate match FIFO looks for the ||R|| column (simultaneous /R/ code groups on
all four channels) and deletes or inserts ||R|| columns to prevent the rate match
FIFO from overflowing or under running. The rate match FIFO can insert or delete as
many ||R|| columns as necessary to perform the rate match operation.
The rx_rmfifodatadeleted and rx_rmfifodatainserted flags that indicate
rate match FIFO deletion and insertion events, respectively, are forwarded to the
FPGA fabric. If an ||R|| column is deleted, the rx_rmfifodeleted flag from each
of the four channels goes high for one clock cycle per deleted ||R|| column. If an
||R|| column is inserted, the rx_rmfifoinserted flag from each of the four
channels goes high for one clock cycle per inserted ||R|| column.
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least three recovered clock
cycles to indicate rate match FIFO full and empty conditions, respectively. You must
then assert the rx_digitalreset signal to reset the receiver PCS blocks.
Cyclone IV Device Handbook, Volume 2
1–67