EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 118

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Digital Signal Processing Block
Figure 4–31. Multiplier Sub-Block Within Stratix GX DSP Block
Note to
(1)
4–52
Stratix GX Device Handbook, Volume 1
These signals can be unregistered or registered once to match data path pipelines if required.
Figure
Data B
Data A
4–31:
shiftout B
shiftin B
shiftout A
The DSP block consists of the following elements:
■
■
Multiplier Block
The DSP block multiplier block consists of the input registers, a
multiplier, and pipeline register for pipelining multiply-accumulate and
multiply-add/subtract functions as shown in
ENA
ENA
D
D
Multiplier block
Adder/output block
CLRN
CLRN
clock[3..0]
sign_a (1)
sign_b (1)
shiftin A
aclr[3..0]
ena[3..0]
Q
Q
ENA
D
CLRN
Q
Figure
Optional
Multiply-Accumulate
and Multiply-Add
Pipeline
Result
to Adder
blocks
4–31.
Altera Corporation
February 2005