EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 151
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EP1SGX25CF672C7
Manufacturer Part Number
EP1SGX25CF672C7
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25CF672C7
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
4.38597GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2005
f
During switchover, the PLL VCO continues to run and either slows down
or speeds up, generating frequency drift on the PLL outputs. The clock
switchover transitions without any glitches. After the switch, there is a
finite resynchronization period to lock onto new clock as the VCO ramps
up. The exact amount of time it takes for the PLL to relock relates to the
PLL configuration and may be adjusted by using the programmable
bandwidth feature of the PLL. The preliminary specification for the
maximum time to relock is 100 µs.
For more information on clock switchover, see AN313: Implementing
Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change
Stratix GX device enhanced PLL counters and delay elements without
reloading a Programmer Object File (.pof). This provides considerable
flexibility for frequency synthesis, allowing real-time PLL frequency and
output clock delay variation. You can sweep the PLL output frequencies
and clock delay in prototype environments. The PLL reconfiguration
feature can also dynamically or intelligently control system clock speeds
or t
Clock delay elements at each PLL output port implement variable delay.
Figure 4–53
for the counters and the clock delay elements. The configuration time is
less than 20 μs for the enhanced PLL using a input shift clock rate of
25 MHz. The charge pump, loop filter components, and phase shifting
using VCO phase taps cannot be dynamically adjusted.
CO
requiring a system-controlled switchover between frequencies of
operation. You can use clkswitch together with the lock signal to
trigger the switch from a clock that is running but becomes unstable
and cannot be locked onto.
delays in end systems.
shows a diagram of the overall dynamic PLL control feature
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
4–85