EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 153
![IC STRATIX GX FPGA 25KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX25CF672C7
Manufacturer Part Number
EP1SGX25CF672C7
Description
IC STRATIX GX FPGA 25KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX25CF672C7
Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
455
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
25660
# I/os (max)
455
Frequency (max)
4.38597GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
25660
Ram Bits
1944576
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX25CF672C7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 153 of 272
- Download datasheet (3Mb)
Altera Corporation
February 2005
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). See
Figure 4–54. External Clock Outputs for PLLs 5 & 6
Notes to
(1)
(2)
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
e 0 Counter
e 1 Counter
e 2 Counter
e 3 Counter
Each external clock output pin can be used as a general purpose output pin from
the logic array. These pins are multiplexed with IOE outputs.
Two single-ended outputs are possible per output counter—either two outputs of
the same frequency and phase or one shifted 180°.
Figure
4–54:
4
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
Stratix GX Device Handbook, Volume 1
(2)
Figure
4–54.
Stratix GX Architecture
extclk0_a
extclk0_b
extclk1_a
extclk1_b
extclk2_a
extclk2_b
extclk3_a
extclk3_b
4–87
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