EP1SGX25CF672C7 Altera, EP1SGX25CF672C7 Datasheet - Page 164

• Manufacturer Part Number: EP1SGX25CF672C7
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C7

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 4.38597GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

I/O Structure
Figure 4–59. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
4–98
Stratix GX Device Handbook, Volume 1
The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0],
four clocks io_clk[3..0], and four clear signals io_bclr[3..0].
The 28 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables
io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear
signals io_cclr[3..0].
Interconnect
Figure
LAB Local
R4, R8 & R24
Interconnects
4–59:
to Adjacent LAB
Interconnect
Direct Link
LAB
io_dataouta[3..0]
io_dataoutb[3..0]
C4, C8 & C16
Interconnects
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
I/O Interconnect
io_clk[7:0]
16
28
from I/O Interconnect (1)
16 Control Signals
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Altera Corporation
28 Data & Control
Signals from
Logic Array (2)
February 2005