EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 11
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
Quantity:
3 000
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Logic Array
Blocks
Altera Corporation
May 2007
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Table 2–1. Stratix II Device Resources
Device
Columns/Blocks
M512 RAM
11 / 930
4 / 104
6 / 202
7 / 329
8 / 488
9 / 699
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks.
the resources available in Stratix II devices.
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency.
Columns/Blocks
M4K RAM
4 / 144
5 / 255
6 / 408
7 / 609
8 / 768
3 / 78
Figure 2–2
M-RAM
Blocks
0
1
2
4
6
9
shows the Stratix II LAB structure.
Columns/Blocks
DSP Block
Stratix II Device Handbook, Volume 1
2 / 12
2 / 16
3 / 36
3 / 48
3 / 63
4 / 96
®
Columns
II Compiler places
Stratix II Architecture
LAB
100
30
49
62
71
81
Table 2–1
LAB Rows
26
36
51
68
87
96
lists
2–3
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