EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 61
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 61 of 238
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Figure 2–36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
Altera Corporation
May 2007
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
8
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
IO_CLKL[7:0]
24 Clocks in the
24 Clocks in the
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable/disable)
8
Quadrant
Quadrant
IO_CLKB[7:0]
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
8
IO_CLKJ[7:0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7:0]
Stratix II Device Handbook, Volume 1
8
IO_CLKI[7:0]
8
8
8
8
8
Stratix II Architecture
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
I/O Clock Regions
2–53
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