EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 173
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
Quantity:
3 000
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Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
t
t
t
t
C L K L
C L K H
M 5 1 2 R C
M 5 1 2 W E R E S U
M 5 1 2 W E R E H
M 5 1 2 D ATA S U
M 5 1 2 D ATA H
M 5 1 2 WA D D R S U
M 5 1 2 WA D D R H
M 5 1 2 R A D D R S U
M 5 1 2 R A D D R H
Table 5–39. DSP Block Internal Timing Microparameters (Part 2 of 2)
Table 5–40. M512 Block Internal Timing Microparameters (Part 1 of 2)
Symbol
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Symbol
Table
5–39:
Synchronous read cycle
time
Write or read enable
setup time before clock
Write or read enable
hold time after clock
Data setup time before
clock
Data hold time after
clock
Write address setup
time before clock
Write address hold time
after clock
Read address setup
time before clock
Read address hold time
after clock
Minimum clock low
time
Minimum clock high
time
Parameter
Parameter
2,089 2,318 2,089 2.433 1,989
Min
203
203
203
203
(4)
22
22
22
22
Grade
1,190
1,190
-3 Speed
Min
(3)
Grade
-3 Speed
Max
(2)
Max
(1)
Min
213
213
213
213
(4)
1,249
1,249
23
23
23
23
Grade
-3 Speed
Min
(3)
Grade
-3 Speed
Max
(3)
Max
(2)
Stratix II Device Handbook, Volume 1
2,089
Min
1,368
1,368
1,368
1,368
233
233
233
233
233
233
233
233
(5)
25
25
25
25
25
25
25
25
Min
-4 Speed
(4)
DC & Switching Characteristics
-4 Speed
Grade
Note (1)
Grade
2,664 2,089 3,104
Max
Max
1,594
1,594
Min
272
272
272
272
Min
(4)
29
29
29
29
(3)
-5 Speed
-5 Speed
Grade
Grade
Max
Max
5–37
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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