EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 171
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 171 of 238
- Download datasheet (3Mb)
Altera Corporation
April 2011
Notes to
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
t
t
t
t
S U
H
C O
P I N 2 C O M B O U T _ R
P I N 2 C O M B O U T _ C
C O M B I N 2 P I N _ R
C O M B I N 2 P I N _ C
C L R
P R E
C L K L
C L K H
Table 5–38. IOE Internal Timing Microparameters
Symbol
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table
5–38:
IOE input and output
register setup time
before clock
IOE input and output
register hold time after
clock
IOE input and output
register clock-to-
output delay
Row input pin to IOE
combinational output
Column input pin to
IOE combinational
output
Row IOE data input to
combinational output
pin
Column IOE data
input to combinational
output pin
Minimum clear pulse
width
Minimum preset pulse
width
Minimum clock low
time
Minimum clock high
time
Parameter
1,101 2,026 1,101 2,127 1,049
Min
122
410
428
991
200
600
600
(3)
101
200
72
Grade
-3 Speed
1,854
Max
(1)
169
760
787
Min
410
428
991
210
630
630
128
101
210
(3)
Grade
75
-3 Speed
1,946
Max
(2)
177
798
825
Stratix II Device Handbook, Volume 1
1,101
Min
140
140
101
391
410
428
944
991
229
229
229
229
690
690
690
690
408
(4)
82
82
97
-4 Speed
DC & Switching Characteristics
Grade
2,329 1,101 2,439
2,131
Max
194
873
904
Min
163
410
428
991
268
268
804
804
(3)
101
96
-5 Speed
Grade
1,018
1,054
2,246
Max
226
5–35
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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