EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 91
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
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Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
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Figure 2–56. DQS Phase-Shift Circuitry
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
May 2007
to IOE
DQSn
Pin
Δt
There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are
up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
The Δt module represents the DQS logic block.
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-
shift circuitry.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Figure
to IOE
DQS
Pin
Δt
2–56:
f
to IOE
DQSn
Pin
Δt
These dedicated circuits combined with enhanced PLL clocking and
phase-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have several levels of drive strength that the
user can control. The default setting used in the Quartus II software is the
maximum current strength setting that is used to achieve maximum I/O
performance. For all I/O standards, the minimum setting is the lowest
drive strength that guarantees the I
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
to IOE
DQS
Pin
Δt
Notes
CLK[15..12]p (2)
Phase-Shift
Circuitry
(1), (2), (3),
DQS
From PLL 5 (3)
to IOE
DQS
Pin
(4)
Δt
OH
DQSn
to IOE
Pin
Stratix II Device Handbook, Volume 1
Δt
/I
OL
of the standard. Using
to IOE
DQS
Pin
Δt
Stratix II Architecture
to IOE
DQSn
Pin
Δt
DQS Logic
Blocks
2–83
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