EP2S60F672C4 Altera, EP2S60F672C4 Datasheet - Page 174
![IC STRATIX II FPGA 60K 672-FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP2S60F672C4
Manufacturer Part Number
EP2S60F672C4
Description
IC STRATIX II FPGA 60K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F672C4
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
492
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1127
EP2S60F672C4ES
EP2S60F672C4ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F672C4
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP2S60F672C4N
Manufacturer:
ALTERA
Quantity:
3 000
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Timing Model
5–38
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
t
t
t
t
t
t
t
t
t
t
M 5 1 2 D ATA C O 1
M 5 1 2 D ATA C O 2
M 5 1 2 C L K L
M 5 1 2 C L K H
M 5 1 2 C L R
M 4 K R C
M 4 K W E R E S U
M 4 K W E R E H
M 4 K B E S U
M 4 K B E H
Table 5–40. M512 Block Internal Timing Microparameters (Part 2 of 2)
Table 5–41. M4K Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Symbol
F
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
MAX
Table
of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
5–40:
Clock-to-output delay
when using output
registers
Clock-to-output delay
without output registers
Minimum clock low time
Minimum clock high time 1,315
Minimum clear pulse
width
Synchronous read cycle
time
Write or read enable
setup time before clock
Write or read enable
hold time after clock
Byte enable setup time
before clock
Byte enable hold time
after clock
Parameter
Parameter
2,102 2,345 2,102 2,461 2,003
1,315
1,462 2,240 1,462 2,351 1,393
Min
298
144
Min
203
203
(4)
(4)
22
22
Grade
Grade
-3 Speed
-3 Speed
Max
Max
(2)
(2)
478
1,380
1,380
Min
298
151
Min
213
213
(4)
(4)
23
23
Grade
Grade
-3 Speed
-3 Speed
Max
Max
(3)
501
(3)
2,102
1,512
1,512
1,512
1,512
1,462
Min
284
298
165
165
Min
233
233
233
233
(5)
(5)
25
25
25
25
Note (1)
-4 Speed
-4 Speed
Grade
Grade
Note (1)
2,695 2,102 3,141
2,575 1,462 3,000
Max
Max
548
1,762
1,762
Altera Corporation
Min
Min
298
192
272
272
(4)
(4)
29
29
-5 Speed
-5 Speed
Grade
Grade
Max
Max
640
April 2011
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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