EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 144

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

PLLs & Clock Networks
4–78
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Number of external clock outputs
Number of feedback clock inputs
Table 4–18. Stratix GX Enhanced PLL & Fast PLL Features (Part 2 of 2)
The maximum count value is 1024, with a 50% duty cycle setting on the counter. The maximum count value for
any other duty cycle setting is 512.
For fast PLLs, m and post-scale counters range from 1 to 32.
The smallest phase shift is determined by the VCO period divided by 8.
For degree increments, Stratix GX devices can shift all output frequencies in increments of at least 45°. Smaller
degree increments are possible depending on the frequency and divide parameters.
PLLs 7 and 8 have two output ports per PLL. PLLs 1 and 2 have three output ports per PLL.
Every Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with eight single-ended or four differential outputs
each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1SGX40 devices each have one single-ended output.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
Every Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback input per
PLL.
Table
Feature
4–18:
Figure 4–48
PLL floorplan.
Four differential/eight singled-ended
or one single-ended
shows a top-level diagram of the Stratix GX device and the
Enhanced PLL
4
(8)
(6)
Notes (1)–(8)
Fast PLL
(7)
Altera Corporation
February 2005