EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 37

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 2–22. Data Path in Parallel Loopback Mode
Altera Corporation
June 2006
Deserializer
Active Path
Non-Active Path
Recovery
Clock
Unit
Serializer
Aligner
Word
BIST PRBS
Channel
Parallel Loopback
The parallel loopback mode exercises the digital logic portion of the
transceiver data path. The analog portions are not use in the loopback
path. The received data is not retimed.
parallel loopback mode. This option is not dynamically switchable.
Reception of an external signal is not possible in this mode.
Reverse Serial Loopback
The reverse serial loopback exercises the analog portion of the
transceiver. This loopback mode is dynamically switchable through the
tx_srlpbk port on a channel by channel basis. Asserting
rxanalogreset in reverse serial loopback mode powers down the
receiver buffer and CRU, preventing data loopback.
the data path in reverse serial loopback mode.
Aligner
Verifier
BIST PRBS
Generator
Encoder
8B/10B
Matcher
Rate
Decoder
Serializer
8B/10B
Byte
Stratix GX Device Handbook, Volume 1
Figure 2–22
Compensation
Deserializer
Phase
FIFO
Byte
Stratix GX Transceivers
shows the data path in
Figure 2–23
Incremental
Verifier
Compensation
BIST
Phase
FIFO
shows
Generator
BIST
2–27