EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 261

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
t
Timing unit interval (TUI)
f
f
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
t
f
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
f
f
f
FALL
HSDR
HSDRDPA
DUTY
LOCK
HSCLK
HSCLK
HSDR
HSCLK_DPA
Table 6–86. High-Speed Timing Specifications & Definitions (Part 2 of 2)
Table 6–87. High-Speed I/O Specifications (Part 1 of 4)
High-Speed Timing Specification
Symbol
/ W
(Clock
=
W = 1 to 30 for
Mbps
W = 2 to 30 for > 717
Mbps
Conditions
Table 6–87
devices.
≤
717
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t
Maximum/minimum LVDS data transfer rate (f
Maximum/minimum LVDS data transfer rate (f
The timing difference between the fastest and slowest output edges,
including t
measurement.
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
shows the high-speed I/O timing specifications for Stratix GX
Min
-5 Speed Grade
10
74
SW
CO
(max) – t
Typ
variation and clock skew. The clock is included in the TCCS
Max
717
717
SW
(min).
C
Notes
/w).
Min
-6 Speed Grade
10
74
Definitions
(1),
Stratix GX Device Handbook, Volume 1
Typ Max
(2)
DC & Switching Characteristics
717
717
HSDR
HSDRDPA
Min
-7 Speed Grade
10
74
= 1/TUI), non-DPA.
Typ Max
= 1/TUI), DPA.
624
717
MHz
MHz
Unit
6–59