EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 17

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Stratix IV GX ES Family Issues
Table 3. Family Issues for Stratix IV GX ES Devices (Part 2 of 3)
March 2011 Altera Corporation
“Dynamic Reconfiguration Issue Between PCIe
Mode and Any Other Transceiver Mode”
The transceiver may not be initialized correctly if
your application uses dynamic reconfiguration to
change the transceiver channel between PCIe mode
and any other transceiver mode.
“Quartus II Mapping Issue with PCIe Interfaces
Using the Hard IP Block”
The Quartus II software incorrectly maps the PCIe
interfaces when using the hard IP block.
“Transmitter PLL Lock (pll_locked) Status Signal”
The transmitter PLL lock status signal
(pll_locked) does not de-assert when the
pll_powerdown signal is asserted in configurations
that use the reference clock pre-divider of 2, 4, or 8.
“Remote System Upgrade”
Remote System Upgrade fails when loading an
invalid configuration image.
“XAUI Functional Mode Failure”
Channel 0 data is shifted by one cycle with respect
to Channels 1, 2, and 3.
“Timing Issue with Two Channels in Basic (PMA
Direct) Configuration”
One particular channel out of a total of 24 channels
(configured in Basic [PMA Direct] mode) on either
side of the device does not close timing for data
rates ≥ 6.375.
“M9K/M144K RAM Block Lock-up”
M9K/M144K RAM blocks may lock up if there is a
glitch in the clock source.
“CRC Error Injection Feature”
The CRC Error Injection feature may not operate
correctly.
“Higher Power Supply Current During Power-Up for
V
Higher power-up current requirements are needed
for V
“M144K Write with Dual-Port Dual-Clock Modes”
M144K RAM blocks may not operate correctly in
dual-port dual-clock modes.
“Automatic Clock Switchover”
Automatic clock switchover feature may not operate
correctly.
CCPD
CCPD
and V
and V
CCA_L/R
CCA_L/R
”
Issue
power supplies.
(ES and Production) Devices
All Stratix IV GX (ES and
All Stratix IV GX (ES and
All Stratix IV GX (ES and
EP4SGX530 ES devices
EP4SGX530 ES devices
EP4SGX530 ES devices
EP4SGX530 ES devices
EP4SGX530 ES devices
EP4SGX530 ES devices
EP4SGX530 ES devices
production) devices
production) devices
EP4SGX230 ES and
EP4SGX230 ES and
EP4SGX230 ES and
EP4SGX230 ES and
production) devices
EP4SGX230 ES and
EP4SGX230 ES and
Affected Devices
All Stratix IV GX
Reconfiguration Issue Between
“Quartus II Mapping Issue with
Errata Sheet for Stratix IV GX Devices
reset workaround in
For more information, refer to
No plan to fix silicon. Apply
No plan to fix silicon. For a
(pll_locked) Status Signal”
Refer to
PCIe Mode and Any Other
PCIe Interfaces Using the
soft-fix solution, refer to
“Transmitter PLL Lock
Transceiver
Production devices
Production devices
Production devices
Production devices
Production devices
Production devices
Hard IP Block”
Planned Fix
Table 1 on page 1
None
Mode”.
“Dynamic
Page 17