EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 5

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Production Devices for Stratix IV GX Devices
Figure 1. Reference Clock Pre-Dividers in Transmitter PLLs
March 2011 Altera Corporation
Input Reference
Clock
Transmitter PLL Lock (pll_locked) Status Signal
1
The MAX II Parallel Flash Loader drives out configuration data on the falling edge of
the DCLK. This does not affect you if you use the Max II Parallel Flash Loader as the
configuration controller.
The transmitter PLL lock status signal (pll_locked) does not de-assert when the
pll_powerdown signal is asserted in configurations that use the reference clock
pre-divider of 2, 4, or 8.
transmitter PLLs. This issue impacts the pll_locked status signal in both the CMU
PLL and the ATX PLL.
Designs that implement the recommended transceiver reset sequence described in the
Reset Control and Power Down
could potentially see a link failure after coming out of reset.
Reference Clock
Pre-Divider
/1, /2, /4, /8
Detect
PFD
Lock
Figure 1
Charge Pump
chapter in volume 2 of the Stratix IV Device Handbook
CMU/ATX PLL
Loop Filter
shows the reference clock pre-divider inside
+
/M
VCO
/L
Errata Sheet for Stratix IV GX Devices
High-Speed
CMU0
Clock
pll_locked
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