EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 27

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Stratix IV GX ES Family Issues
March 2011 Altera Corporation
High I/O Pin Leakage Current
Higher Standby Current for V
Reduced M9K/M144K Performance
Reduced Settings for Transceivers
f
If you are using ES devices, review your f
PFD Frequency” in each PLL section of your .fit.rpt compilation report file. If needed,
recompile your design in the Quartus II software with modified PLL settings to
achieve the higher minimum f
For more information about the ALTPLL megafunction, refer to the
Development Software Handbook
Guide.
Top and bottom I/O pin leakage current is higher for Stratix IV GX ES devices than
production devices. Side I/O banks are not affected. Refer to
Stratix IV GX ES device I/O pin leakage current on top and bottom I/O banks.
Table 8. I/O Pin Leakage Current for Top and Bottom I/O Banks
These I/O pin leakage current values apply to ES silicon only and not to production
silicon.
You can expect to see higher standby I
Stratix IV GX ES devices than indicated in the Quartus II software version 9.0 and the
PowerPlay EPE version 9.0. The higher standby I
is fixed in production devices.
Use the PowerPlay EPE version 9.0.1 to estimate current and power/thermal
requirements for the Stratix IV GX ES device. The PowerPlay EPE version 9.0 will not
be updated with these higher standby current values.
M9K/M144K f
than indicated in the Quartus II software version 8.1. Compile your design in the
Quartus II software version 9.0 to estimate the impact on your design.
There are reduced settings for the M counter of the ALTGX TX PLLs and RX CDRs in
the EP4SGX230 ES device transceiver blocks. Settings with M=16 and M=20 in all
ALTGX PLLs are removed from Basic modes and all protocol configurations. These
changes resulted in blocking one configuration for Sonet OC-48 (RefCLK =
77.76 MHz).
Temp.
25°C
85°C
MAX
3.0 V
140
35
and t
CO
CC
performance for Stratix IV GX ES devices may be lower
2.5 V
100
Power Supply
25
IN PFD
or the
I/O Bank Voltage
.
Phase-Locked Loops (ALTPLL) Megafunction User
CC
1.8 V
INPFD
values on the V
15
60
settings by searching under “Nominal
CC
current for the V
1.5 V
11
45
CC
Errata Sheet for Stratix IV GX Devices
power supply for
Table 8
1.2 V
35
9
Quartus II
CC
for
power supply
Units
μA
μA
Page 27