EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 26

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 26
Errata Sheet for Stratix IV GX Devices
Higher V
I/O Jitter
Higher Minimum f
CC
Stratix IV GX ES devices require higher V
Table 7. Power Supply Levels for Stratix IV GX ES Devices
EP4SGX230 ES devices require V
0.95 V +/- 0.03 V for -2 and -2× speed grades only.
EP4SGX530 ES devices require V
0.95 V +/- 0.03 V for all speed grades.
Use the PowerPlay EPE version 9.0.1 to estimate current and power/thermal
requirements for Stratix IV GX ES devices with the required higher power supply
levels. The PowerPlay EPE version 9.0 reflects current and power estimates for
production devices at data sheet specifications only.
Production devices will not operate at these higher power supply levels. If needed,
design your power supplies to support dropping power supply levels back to data
sheet specification for production devices.
There are no reliability issues with Stratix IV GX ES devices at these higher power
supply levels.
Stratix IV GX ES devices may exhibit ± ~100 ps higher than expected jitter on all
non-transceiver I/O pins. The actual amount of additional jitter is application and
toggle-rate dependent. High-speed transceiver I/O pins are unaffected and perform
to data sheet specifications.
Altera has fixed the issue in production devices, which meets all current jitter
specifications.
If you are using ES devices, you need to account for this additional timing uncertainty
in all non-transceiver I/O timing closure budgets.
Stratix IV GX ES devices may exhibit higher than expected PLL jitter at low f
settings. Raising the minimum f
ES devices.
Altera has fixed the issue in production devices, which meets the current f
minimum of 5 MHz.
V
V
V
V
CC
CCD_PLL
CCHIP_L
CCHIP_R
Power Supply
Power Supply Levels
INPFD
Setting
Power Supply
Level (V)
0.95
0.95
0.95
0.95
INPFD
CC
CC
Core voltage and periphery circuitry power supply
PLL digital power supply
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
, V
, V
CCD_PLL
CCD_PLL
to 25 MHz removes the additional PLL jitter in
CC
power supply levels (refer to
, and V
, and V
CCH IP_L/R
CCH IP_L/R
Description
March 2011 Altera Corporation
Stratix IV GX ES Family Issues
power supplies set to
power supplies set to
Table
INPFD
INPFD
7).