EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 25

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Stratix IV GX ES Family Issues
Table 6. Updated Data Rate Ranges and Behavior for Affected Configurations with Stratix IV GX ES Devices (Part 2 of 2)
March 2011 Altera Corporation
PMA direct mode ×N with CMU PLL or ATX
PLL
PCIe Gen2 ×8 using CMU PLL or ATX PLL
PCIe Gen2 ×4 functional mode using ATX
PLL
(OIF) CEI PHY interface functional mode with
ATX PLL
Basic functional mode ×1/×4/×8 with ATX
PLL
Notes to
(1) The ATX PLL will be supported in the PCIe Compiler version 9.1.
(2) The updated data rate ranges and behaviors shown in
transmit PLL used by the transceiver:
a. CMU PLL—the CMU PLL must be placed in the center transceiver block for a PMA direct mode ×N link and on the lower transceiver block
for a Basic ×8 (PCS+PMA Bonded) link
b. ATX PLL—the transceiver channel must be placed in the adjacent transceiver block in Basic functional mode ×1/×4 and below the center
transceiver block for PMA direct mode ×N
Table
Endpoints Using the Hard IP Implementation Incorrectly Handle CfgRd0
6:
f
Configuration
This issue is modeled starting from Quartus II software version of 9.0 SP1 for the
impacted ES devices. You must recompile your design and if the transceiver
configuration is one of the impacted configurations as listed above, Quartus II version
9.0 SP1 will generate a compilation error. The error message conveys the actions
needed for this issue.
For more information about this issue, refer to the Endpoints Using the Hard IP
Implementation Incorrectly Handle CfgRd0 section of the
Notes and Errata
document.
If CMU PLL is used and:
■
■
If ATX PLL is used and:
■
■
Contact Altera Technical Support.
Use PCIe Gen2 ×4 functional mode using CMU PLL only.
3.125 Gbps to 5.4 Gbps for -2, -2×, and -3 speed grades.
Up to 5.4 Gbps for -2, -2×, and -3 speed grades.
if the number of contiguous bonded channels is ≤ 17 (2):
■
■
if the number of contiguous bonded channels is > 17:
■
if the number of contiguous bonded channels is ≤ 12 (2):
■
if the number of contiguous bonded channels is > 12:
■
Table 6
5 Gbps to 6.5 Gbps (-2 speed grade with higher transceiver power
supplies. V
be set to 1.2 ± 0.05 V)
600 Mbps to 5 Gbps (-2, -2x, -3, and -4 speed grade)
600 Mbps to 3.25 Gbps (-2, -2x, -3, and -4 speed grades)
up to 5.4 Gbps (-2, -2x, and -3 speed grades)
up to 3.25 Gbps (-2, -2x, and -3 speed grades)
require the following specific placement constraints, depending on the type of
CCR_L/R
Updated Data Rate Ranges and Behavior
, V
CCT_L/R
, and V
MegaCore IP Library Release
CCL_GXB_L/Rn
Errata Sheet for Stratix IV GX Devices
(2)
power supplies must
(2)
Page 25