EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 8

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 8
Table 2. Maximum Data Rate Specification in ALTGX Functional Modes Impacted by ×N Clock Line Timing Issue (Part 1
of 2)
Errata Sheet for Stratix IV GX Devices
Basic ×8
Basic ×1 and
Basic ×4
Functional
ALTGX
Mode
×8 and ×N Clock Line Timing Issue for Transceivers
ATX PLL (6G)
ATX PLL (6G)
TX PLL Type
CMU PLL
The ×N clock line timing issue in Stratix IV GX production devices affects the
maximum data rate supported in the following transceiver configurations:
■
■
■
■
The maximum supported data rate in these configurations depends on:
■
■
■
■
Table 2
Basic ×8 functional mode using CMU PLL or ATX PLL (6G)
Basic ×1 and Basic ×4 functional mode using ATX PLL (6G)
Basic (PMA Direct) ×N functional mode using CMU PLL or ATX PLL (6G)
(OIF) CEI PHY Interface functional mode using ATX PLL (6G)
Transmitter PLL type (CMU PLL or ATX PLL [6G])
Device speed grade
V
1
Physical distance between the transmitter PLL and the transceiver channel (Refer
to the Placement Restrictions column in
CCL_GXB
specifies the maximum data rate supported in the affected configurations.
Up to ×8
Up to ×8
Up to ×4
Bonding
The voltage supply levels can be 1.1 V or 1.2 V, depending on the data rate.
/V
CCT
Speed Grade
/V
C2/C3/I3
All
All
CCR
All
(2)
(2)
power supply level
Supported Data Rates
Supply Level
V
1.2 ± 0.05
V
CCT
CCL_GXB
(V)
1.1
1.1
1.1
/V
(1)
CCR
/
Table
Rate (Gbps)
2)
Max Data
5.0
6.5
6.5
6.5
Production Devices for Stratix IV GX Devices
You must use the ATX PLL
(6G) between the two
transceiver blocks. For more
information, refer to
Figure
You must use the ATX PLL
(6G) adjacent to the
transceiver block where the
channels are located. For
more information, refer to
Figure
March 2011 Altera Corporation
Placement Restrictions
4.
5.
—