XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 390

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
390
3-State Signal Clock Enable – TCE
Reset Input – SR
TCE is an active High clock enable for the 3-state control path.
The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains
to be driven LOW asynchronously. For circuits in the OSERDES running on the CLK
domain where timing is critical, there is an internal, dedicated circuit to re-time the SR
input to produce a reset signal synchronous to the CLK domain. Similarly, there is also a
dedicated circuit to re-time the SR input to produce a reset signal synchronous to the
CLKDIV domain. Because there are circuits in the OSERDES that re-time the SR input, the
user is only required to provide a reset pulse to the SR input that meets timing on the
CLKDIV frequency domain (synchronous to CLKDIV). Therefore, SR should be driven
High for a minimum of one CLKDIV cycle.
When building an interface consisting of multiple OSERDES, it may be important that all
OSERDES in the interface are synchronized to one another. The internal re-timing of the SR
input guarantees that all OSERDES that receive the same reset pulse come out of reset in
sync with one another. The reset timing of multiple OSERDES is shown in
Figure 8-16: Two OSERDES Coming Out of Reset Synchronously with One Another
Clock Event 1
A reset pulse is generated on the rising edge of CLKDIV. Because the pulse must take two
different routes to get to OSERDES0 and OSERDES1, there are different propagation
delays for both paths. The difference in propagation delay is emphasized in
The path to OSERDES0 is very long and the path to OSERDES1 is very short, such that
each OSERDES receives the reset pulse in a different CLK cycle. The internal resets for both
CLK and CLKDIV go into reset asynchronously when the SR input is asserted.
Internal Reset
Internal Reset
(CLKDIV)
Signal at
SR Input
(CLK)
www.xilinx.com
OSERDES0
OSERDES1
OSERDES0
OSERDES1
OSERDES0
OSERDES1
CLKDIV
CLK
Event 1
Clock
Event 2
Clock
Event 3
Clock
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Clock
Event 4
UG070_c8_24_041007
Figure
Figure
8-16.
8-16.
R