XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 5

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

UG070 (v2.6) December 1, 2008
01/04/07
03/15/07
(cont’d)
Date
Version
(cont’d)
2.0
2.1
•
•
•
•
•
•
•
•
• Added new section
•
Chapter 8, “Advanced SelectIO Logic
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
“ILOGIC
ILOGIC/ISERDES and OLOGIC/OSERDES.
Figure
Figure
“DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI
link requirements and reference to on-chip differential termination.
“DCI in Virtex-4 FPGA
resistors are not required.
“PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and
recommending against using these circuits to drive a logic level on a board-level trace.
“Frequency Synthesizer
AUTOCALIBRATE and CONFIG STEPPING.
including VHDL/Verilog source files in UG070.zip.
Table
Table
Table
“Registered Outputs – Q1 to
“High-Speed Clock for Strobe-Based Memory Interfaces –
to ground OCLK when INTERFACE_TYPE is NETWORKING.
“BITSLIP_ENABLE
INTERFACE_TYPE.
“INTERFACE_TYPE
is in Memory Mode. Added
Memory Mode.
Added section
“ISERDES Width
ISERDES use with differential/single-ended inputs.
“Guidelines for Expanding the Serial-to-Parallel Converter Bit
number of master/slave and input/output reversals.
“Verilog Instantiation Template to use Width Expansion
of errors in the template.
“ISERDES
replaced with statement relating latency to INTERFACE_TYPE.
Deleted synthesis translate_off/synthesis translate_on statements
from all ISERDES instantiation templates.
“Data Parallel-to-Serial
OSERDES prior to use.
“OSERDES Width
OSERDES use with differential/single-ended outputs.
“OSERDES VHDL Template” in Chapter
TRISTATE_WIDTH.
6-41: Added SSO data for FF676 device/package combinations.
7-1: Removed OFB/TFB inputs and associated MUXes.
8-2: Removed OFB/TFB inputs.
8-1: REV: Added instruction to connect to GND.
8-2: Corrected BITSLIP_ENABLE value from “String” to “Boolean”.
Resources”: Added sentence clarifying SR and REV sharing between
Latencies”: Deleted former Table 8-4 and most of the text in this section and
“ISERDES Clocking Methods.”
“FIFO16 Error Condition and Work-Arounds” in Chapter
Expansion”: Added explanatory paragraph regarding master/slave
Expansion”: Added explanatory paragraph regarding master/slave
www.xilinx.com
Hardware”: Modified point 3 detailing when VRP/VRN reference
Attribute”: Specified setting according to setting of
Attribute”: Added recommendation to use MIG when ISERDES
Characteristics”: Updated information regarding the setting of
Converter”: Added recommendation to apply a reset to
Figure 8-6
Q6”: Added clarification on bit in/out sequence.
Resources”:
Revision
to illustrate ISERDES internal connections in
8: Removed erroneous semicolon following
Usage”: Removed incorrect bidirectional
IOBUF”: Added a paragraph
Feature”: Corrected a number
OCLK”: Added instruction
Virtex-4 FPGA User Guide
Width”: Corrected a
4,