XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 64

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
64
Status or Dynamic Reconfiguration Data Output — DO[15:0]
Dynamic Reconfiguration Ready Output — DRDY
The DO output bus provides DCM status or data output when using dynamic
reconfiguration
available in the Dynamic Reconfiguration chapter of the
more information.
If the dynamic reconfiguration port is not used, using DCM_BASE or DCM_PS instead of
DCM_ADV is strongly recommended.
Table 2-5: DCM Status Mapping to DO Bus
When LOCKED is Low (during reset or the locking process), all the status signals deassert
Low.
The dynamic reconfiguration ready (DRDY) output pin provides the response to the DEN
signal for the DCM’s dynamic reconfiguration feature. Further information on the DRDY
pin is available in the dynamic reconfiguration section in the
DO[0]
DO[1]
DO[2]
DO[3]
DO[15:4]
DO Bit
Phase-shift overflow
CLKIN stopped
CLKFX stopped
CLKFB stopped
Not assigned
(Table
Status
2-5). Further information on using DO as the data output is
www.xilinx.com
Asserted when the DCM is phase-shifted beyond the
allowed phase-shift value or when the absolute delay
range of the phase-shift delay line is exceeded.
Asserted when the input clock is stopped (CLKIN
remains High or Low for one or more clock cycles).
When CLKIN is stopped, the DO[1] CLKIN stopped
status is asserted within nine CLKIN cycles. When
CLKIN is restarted, CLK0 starts toggling and DO[1] is
deasserted within nine clock cycles.
Asserted when CLKFX stops. The DO[2] CLKFX
stopped status is asserted within 257 to 260 CLKIN
cycles after CLKFX stopped. CLKFX will not resume,
and DO[2] is not deasserted until the DCM is reset.
Asserted when the feedback clock is stopped (CLKFB
remains High or Low for one or more clock cycles). The
DO[3] CLKFB stopped status is asserted within six
CLKIN cycles after CLKFB is stopped. CLKFB stopped
is deasserted within six CLKIN cycles when CLKFB
resumes after being stopped momentarily. An
occasionally skipped CLKFB will not affect the DCM
operation. However, stopping CLKFB for a long time
can result in the DCM losing LOCKED. When LOCKED
is lost, the DCM needs to be reset to resume operation.
Virtex-4 Configuration Guide
Description
UG070 (v2.6) December 1, 2008
Virtex-4 Configuration
Virtex-4 FPGA User Guide
Guide.
for
R