XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 49

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
BUFGMUX and BUFGMUX_1 VHDL and Verilog Templates
R
Verilog Template
Declaring Constraints in UCF File
VHDL Template
The following examples illustrate the instantiation of the BUFGMUX module in VHDL
and Verilog. The instantiation of BUFGMUX_1 is exactly the same as BUFGMUX with
exception of the primitive name.
//Example BUFGCE module declaration
module BUFGCE (O, CE, I);
endmodule;
//Example BUFGCE instantiation
BUFGCE U_BUFGCE (
.O(user_o),
.CE0(user_ce),
.I0(user_i)
);
// Declaring constraints in Verilog
// synthesis attribute LOC of U_BUFGCE is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
INST "U_BUFGCE" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
--Example BUFGMUX declaration
component BUFGMUX
port(
end component;
--Example BUFGMUX instantiation
U_BUFGMUX : BUFGMUX
Port map (
--Declaring constraints in VHDL file
attribute LOC : string;
attribute LOC of U_BUFGMUX: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
output O;
input CE;
input I;
O: out std_ulogic;
I0: in
I1
S: in
);
O => user_o,
I0 => user_i0,
I1 => user_i1,
S => user_s
);
std_ulogic
std_ulogic;
: in
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std_ulogic;
VHDL and Verilog Templates
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