XC4VFX40-11FFG672C Xilinx Inc, XC4VFX40-11FFG672C Datasheet - Page 180

• Manufacturer Part Number: XC4VFX40-11FFG672C
• Description: IC FPGA VIRTEX-4 FX 40K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-11FFG672C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
180
Error Status Description
Block RAM ECC Attribute
Block RAM ECC VHDL and Verilog Templates
Block RAM ECC VHDL Template
The block RAM ECC is able to detect single- and double-bit errors from the block RAM.
However, only the single-bit error can be corrected. The ECC logic does not correct the bit
in the actual block RAM storage location. If the block RAM location containing the bit error
is not overwritten, then further reads from that location causes the ECC logic to continue to
correct the error.
Table 4-18: STATUS Bit Truth Table
In addition to the built-in registers in the decode and correct logic, the RAMB32_S64_ECC
primitive allows the use of optional pipeline registers to produce higher performance with
one additional latency. Valid values for the DO_REG attribute are 0 or 1.
VHDL and Verilog templates are available in the Libraries Guide.
STATUS[1:0]
-- RAMB32_S64_ECC: To incorporate this function into the design,
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Library UNISIM;
use UNISIM.vcomponents.all;
-- <---Cut code below this line and paste into the architecture body-->
00
01
10
11
-- RAMB32_S64_ECC: Virtex-4 512 x 64 Error Correction Block RAM
-- Virtex-4 FPGA User Guide
Copy the following two statements and paste them before the
Entity declaration, unless they already exists.
declaration : instance name (RAMB32_S64_ECC_inst) and/or the port
declaration : use declaration statement for the UNISIM.v
instance
primitives : component declarations for all Xilinx primitives
Library
Xilinx
VHDL
code
for
Table 4-18
No bit error.
Single-bit error. The block RAM ECC macro detects and automatically
corrects a single-bit error.
Double-bit error. The block RAM ECC macro detects a double-bit error.
Undefined, not a valid status error.
: the following instance declaration needs to be placed
: in the architecture body of the design code. The
: declarations after the "=>" assignment can be changed
: to properly connect this function to the design.
: All inputs and outputs must be connected.
: In addition to adding the instance declaration, a
: components library needs to be added before the
: entity declaration. This library contains the
: and points to the models that will be used for
: simulation.
www.xilinx.com
is the truth table for the STATUS bits.
Description
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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