XC4VFX40-11FFG672C Xilinx Inc, XC4VFX40-11FFG672C Datasheet - Page 257

• Manufacturer Part Number: XC4VFX40-11FFG672C
• Description: IC FPGA VIRTEX-4 FX 40K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-11FFG672C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
LVDCI (Low Voltage Digitally Controlled Impedance)
Table 6-4
LVCMOS15 I/O standards.
Table 6-4: Allowed Attributes for the LVCMOS18 and LVCMOS15 I/O Standard
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as LVTTL,
LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of
the driven line. Virtex-4 devices provide a controlled impedance output driver to provide
series termination without external source termination resistors. The impedance is set by
the common external reference resistors, with resistance equal to the trace characteristic
impedance, Z
Sample circuits illustrating both unidirectional and bidirectional termination techniques
for a controlled impedance driver are shown in
standards supporting a controlled impedance driver are: LVDCI_15, LVDCI_18,
LVDCI_25, and LVDCI_33.
IOSTANDARD
CAPACITANCE
DRIVE
SLEW
Figure 6-29: Controlled Impedance Driver with Unidirectional Termination
Figure 6-30: Controlled Impedance Driver with Bidirectional Termination
Attributes
R 0 = R VRN = R VRP = Z 0
details the allowed attributes that can be applied to the LVCMOS18 and
LVDCI
0
.
R 0 = R VRN = R VRP = Z 0
LVDCI
Specific Guidelines for Virtex-4 FPGA I/O Supported Standards
www.xilinx.com
IBUF/IBUFG
LVCMOS18
LVCMOS15
IOB
IOB
UNUSED
UNUSED
LOW, NORMAL, DONT_CARE
Z 0
Z 0
Figure 6-29
OBUF/OBUFT
2, 4, 6, 8, 12, 16
{FAST, SLOW}
LVCMOS18
LVCMOS15
Primitives
IOB
IOB
R 0 = R VRN = R VRP = Z 0
and
Figure
LVDCI
UG070_6_29_031308
6-30. The DCI I/O
LVDCI
2, 4, 6, 8, 12, 16
{FAST, SLOW}
UG070_6_30_031308
LVCMOS18
LVCMOS15
IOBUF
257