XC4VFX40-11FFG672C Xilinx Inc, XC4VFX40-11FFG672C Datasheet - Page 61

• Manufacturer Part Number: XC4VFX40-11FFG672C
• Description: IC FPGA VIRTEX-4 FX 40K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-11FFG672C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 352
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Control and Data Input Ports
R
Reset Input — RST
Phase-Shift Increment/Decrement Input — PSINCDEC
Phase-Shift Enable Input — PSEN
Dynamic Reconfiguration Data Input — DI[15:0]
Dynamic Reconfiguration Address Input — DADDR[6:0]
The reset (RST) input pin resets the DCM circuitry. The RST signal is an active High
asynchronous reset. Asserting the RST signal asynchronously forces all DCM outputs Low
(the LOCKED signal, all status signals, and all output clocks) after some propagation delay.
When the reset is asserted, the last cycle of the clocks can exhibit a short pulse and a
severely distorted duty-cycle, or no longer be deskewed with respect to one another while
deasserting Low. Deasserting the RST signal starts the locking process at the next CLKIN
cycle.
To ensure a proper DCM reset and locking process, the RST signal must be held until the
CLKIN and CLKFB signals are present and stable for at least 200 ms. (The 200 ms
requirement for CLKFB only applies when external feedback is used.)
The time it takes for the DCM to lock after a reset is specified in the
LOCK_DLL (for a DLL output) and LOCK_FX (for a DFS output). These are the CLK and
CLKFX outputs described in
frequencies. The worse-case numbers are specified in the
the DCM must be held in reset until CLKIN is stable.
The phase-shift increment/decrement (PSINCDEC) input signal must be synchronous
with PSCLK. The PSINCDEC input signal is used to increment or decrement the phase-
shift factor when PSEN is activated. As a result, the output clocks are shifted. The
PSINCDEC signal is asserted High for increment or deasserted Low for decrement. This
input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE
or FIXED.
The phase-shift enable (PSEN) input signal must be synchronous with PSCLK. A variable
phase-shift operation is initiated by the PSEN input signal. It must be activated for one
period of PSCLK. After PSEN is initiated, the phase change is gradual with completion
indicated by a High pulse on PSDONE. There are no sporadic changes or glitches on any
output during the phase transition. From the time PSEN is enabled until PSDONE is
flagged, the DCM output clock moves bit-by-bit from its original phase shift to the target
phase shift. The phase shift is complete when PSDONE is flagged. PSEN must be tied to
ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE or FIXED.
shows the timing for this input.
The dynamic reconfiguration data (DI) input bus provides reconfiguration data for
dynamic reconfiguration. When not used, all bits must be assigned zeros. See the Dynamic
Reconfiguration chapter of the
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration
address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
The DO output bus will reflect the DCM’s status. See the Dynamic Reconfiguration chapter
of the
Virtex-4 Configuration Guide
www.xilinx.com
“Clock Output
Virtex-4 Configuration Guide
for more information.
Ports”. The DCM locks faster at higher
Virtex-4 Data
for more information.
Virtex-4 Data Sheet
Sheet. In all designs,
DCM Ports
Figure 2-7
as
61