XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 227
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Multiplexer Primitives and Verilog/VHDL Examples
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Template
This section provides generic VHDL and Verilog reference code implementing
multiplexers. These submodules are built from LUTs and the dedicated MUXF5, MUXF6,
MUXF7, and MUXF8 multiplexers. To automatically generate large multiplexers using
these dedicated elements, use the CORE Generator software Bit Multiplexer and Bus
Multiplexer modules.
For applications such as comparators, encoder-decoders or “case” statement in VHDL or
Verilog, these resources offer an optimal solution.
attribute INIT: string;
--
attribute INIT of U_SRLC16E: label is "0000";
--
-- ShiftRegister Instantiation
U_SRLC16E: SRLC16E
// Module: SHIFT_REGISTER_16
// Description: Verilog instantiation template
// Cascadable 16-bit Shift Register with Clock Enable (SRLC16E)
// Device: Virtex-4 Family
//-------------------------------------------------------------------
D
CE
CLK
A0
A1
A2
A3
Q
Q15
);
defparam
SRLC16E U_SRLC16E
port map (
=> , -- insert input signal
=> , -- insert Clock Enable signal (optional)
=> , -- insert Clock signal
=> , -- insert Address 0 signal
=> , -- insert Address 1 signal
=> , -- insert Address 2 signal
=> , -- insert Address 3 signal
=> , -- insert output signal
=>
);
-- insert cascadable output signal
www.xilinx.com
(
.D(),
.A0(),
.A1(),
.A2(),
.A3(),
.CLK(),
.CE(),
.Q(),
.Q15()
Multiplexer Primitives and Verilog/VHDL Examples
227
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