XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 330
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 7: SelectIO Logic Resources
330
ILOGIC Timing Characteristics, DDR
Clock Event 4
•
Figure 7-10
used, T
OPPOSITE_EDGE mode. For other modes, add the appropriate latencies as shown in
Figure 7-7, page
Clock Event 1
•
•
Clock Event 2
•
Clock Event 9
•
(Reset)
CLK
CE1
T
SR
Q1
Q2
IDOCK
At time T
this case) becomes valid-High resetting the input register and reflected at the Q1
output of the IOB at time T
At time T
High at the CE1 input of both of the DDR input registers, enabling them for incoming
data. Since the CE1 and D signals are common to both DDR registers, care must be
taken to toggle these signals between the rising edges and falling edges of CLK as
well as meeting the register setup-time relative to both clocks.
At time T
valid-High at the D input of both registers and is reflected on the Q1 output of input-
register 1 at time T
At time T
valid-Low at the D input of both registers and is reflected on the Q2 output of input-
register 2 at time T
At time T
this case) becomes valid-High resetting IFF1 (Q1) at time T
and IFF2 (Q2) at time T
D
T
IDOCK
ICKQ
illustrates the ILOGIC in IDDR mode timing characteristics. When IDELAY is
ISRCK
ISRCK
Figure 7-10: ILOGIC in IDDR Mode Timing Characteristics
ICE1CK
IDOCK
IDOCK
is replaced by T
1
326.
T
ICE1CK
before Clock Event 4, the SR signal (configured as synchronous reset in
before Clock Event 9, the SR signal (configured as synchronous reset in
before Clock Event 1 (rising edge of CLK), the input signal becomes
before Clock Event 2 (falling edge of CLK), the input signal becomes
before Clock Event 1, the input clock enable signal becomes valid-
2
T
ICKQ
ICKQ
IDOCK
www.xilinx.com
ICKQ
after Clock Event 1.
after Clock Event 2 (no change in this case).
3
IDOCKD
ICKQ
(OPPOSITE_EDGE Mode)
after Clock Event 10.
4
after Clock Event 4.
. The example shown uses IDDR in
5
T
ICKQ
6
7
UG070 (v2.6) December 1, 2008
8
ICKQ
Virtex-4 FPGA User Guide
after Clock Event 9,
9
10
T
T
ISRCK
ICKQ
UG070_7_10_072904
11
T
ICKQ
R
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