XC4VFX40-11FFG1152C Xilinx Inc, XC4VFX40-11FFG1152C Datasheet - Page 37
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XC4VFX40-11FFG1152C
Manufacturer Part Number
XC4VFX40-11FFG1152C
Description
IC FPGA VIRTEX-4 FX 40K 1152FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX40-11FFG1152C
Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX40-11FFG1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CE
I0
I1
O
S
1
at I0
R
T
BCCKO_O
BUFGMUX_VIRTEX4 with a Clock Enable
A BUFGMUX_VIRTEX4 with a clock enable BUFGCTRL configuration allows the user to
choose between the incoming clock inputs. If needed, the clock enable is used to disable
the output.
shows the timing diagram.
In
•
•
•
•
Figure 1-16: BUFGMUX_VIRTEX4 with a CE Timing Diagram
Figure
At time event 1, output O uses input I0.
Before time event 2, S is asserted High.
At time T
to Low transition of I0 followed by a High to Low transition of I1 is completed.
At time T
switched Low and kept at Low after a High to Low transition of I1 is completed.
CE
1-16:
I1
I0
S
Figure 1-15
Figure 1-15: BUFGMUX_VIRTEX4 with a CE and BUFGCTRL
BUFGMUX_VIRTEX4+CE
BCCKO_O
BCCCK_CE
2
Design Example
Begin I1
, after time event 2, output O uses input I1. This occurs after a High
, before time event 3, CE is asserted Low. The clock output is
illustrates the BUFGCTRL usage design example and
T
www.xilinx.com
BCCKO_O
O
CE
S
GND
GND
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Clock Off
Global Clocking Resources
3
ug070_1_15_071304
T
BCCCK_CE
Figure 1-16
O
UG070_1_16_082504
37
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