XC4005-5PC84C Xilinx Inc, XC4005-5PC84C Datasheet - Page 13

• Manufacturer Part Number: XC4005-5PC84C
• Description: IC LOGIC CL ARRAY 5000GAT 84PLC
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005-5PC84C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 61
• Number Of Gates: 5000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1068

Detailed Functional Description
XC4000 and XC4000A Input/Output Blocks
(For XC4000H family, see page 2-82)
The IOB forms the interface between the internal logic and
the I/O pads of the LCA device. Under configuration con-
trol, the output buffer receives either the logic signal (.out)
routed from the internal logic to the IOB, or the complement
of this signal, or this same data after it has been clocked
into the output flip-flop.
As a configuration option, each flip-flop (CLB or IOB) is
initialized as either set or reset, and is also forced into this
programmable initialization state whenever the global Set/
Reset net is activated after configuration has been com-
pleted. The clock polarity of each IOB flip-flop can be
configured individually, as can the polarity of the 3-state
control for the output buffer.
Figure 11. XC4000 and XC4000A I/O Block
Boundary
Scan
Ouput Clock OK
Input Clock IK
Ouput Data O
I - capture
I - update
3-State TS
OUTPUT
INPUT
DELAY
OUTPUT
INVERT
M
M
GLOBAL
TS/OE
S/R
Boundary
Scan
M
M
Boundary
INVERT
S/R
Scan
M
M
TS INV
TS - capture
TS - update
INVERT
S/R
O - capture
Q - capture
O - update
D
M
sd
rd
D
Q
sd
rd
Q
Q
L
2-19
FLIP-FLOP/LATCH
OUT
SEL
M
Each output buffer can be configured to be either fast or
slew-rate limited, which reduces noise generation and
ground bounce. Each I/O pin can be configured with either
an internal pull-up or pull down resistor, or with no internal
resistor. Independent of this choice, each IOB has a pull-
up resistor during the configuration process.
The 3-state output driver uses a totem pole n-channel
output structure. V
than V
symmetrical.
Family
XC4000
XC4000A
XC4000H
*XC4000H devices can sink only 4 mA configured for SoftEdge mode
EXTEST
M M
M M
CC
, which makes rise and fall delays more
SLEW
RATE
Per IOB
Source
OH
4
4
4
Input Data 1 I1
Input Data 2 I2
is one n-channel threshold lower
DOWN
PULL
Per IOB
Sink
12
24
24*
PULL
UP
Pair Sink
Per IOB
V
CC
24
48
48
PAD
X3025
# Slew
Modes
2
4
2