XC4005-5PC84C Xilinx Inc, XC4005-5PC84C Datasheet - Page 14

• Manufacturer Part Number: XC4005-5PC84C
• Description: IC LOGIC CL ARRAY 5000GAT 84PLC
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005-5PC84C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 61
• Number Of Gates: 5000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1068

XC4000, XC4000A, XC4000H Logic Cell Array Families
The inputs drive TTL-compatible buffers with 1.2-V input
threshold and a slight hysteresis of about 300 mV. These
buffers drive the internal logic as well as the D-input of the
input flip-flop.
Under configuration control, the set-up time of this flip-flop
can be increased so that normal clock routing does not
result in a hold-time problem. Note that the input flip-flop
set-up time is defined between the data measured at the
device I/O pin and the clock input at the IOB. Any clock
routing delay must, therefore, be subtracted from this set-
up time to arrive at the real set-up time requirement on the
device pins. A short specified set-up time might, therefore,
result in a negative set-up time at the device pins, i.e. a
hold-time requirement, which is usually undesirable. The
default long set-up time can tolerate more clock delay
without causing a hold-time requirement. For faster input
register setup time, with non-zero hold, attach a "NODELAY"
property to the flip-flop. The exact method to accomplish
this depends on the design entry tool.
The input block has two connections to the internal logic,
I1 and I2. Each of these is driven either by the incoming
data, by the master or by the slave of the input flip-flop.
Wide Decoders
The periphery of the chip has four wide decoder circuits at
each edge (two in the XC4000A). The inputs to each
decoder are any of the I1 signals on that edge plus one
local interconnect per CLB row or column. Each decoder
generates High output (resistor pull-up) when the AND
condition of the selected inputs, or their complements, is
true. This is analogous to the AND term in typical PAL
devices. Each decoder can be split at its center.
The decoder outputs can drive CLB inputs so they can be
combined with other logic, or to form a PAL-like AND/OR
structure. The decoder outputs can also be routed directly
to the chip outputs. For fastest speed, the output should be
on the same chip edge as the decoder.
Figure 12. Example of Edge Decoding. Each row or column of
CLBs provide up to three variables (or their complements)
IOB
A
.I1
INTERCONNECT
C
IOB
B
.I1
(
(A • B • C) .....
(A B C) .....
(A B C) .....
C) .....
X2627
2-20
Configurable Logic Blocks
Configurable Logic Blocks implement most of the logic in
an LCA device. Two 4-input function generators (F and G)
offer unrestricted versatility. A third function generator (H)
can combine the outputs of F and G with a ninth input
variable, thus implementing certain functions of up to nine
variables, like parity check or expandable-identity com-
parison of two sets of four inputs.
The four control inputs C1 through C4 can each generate
any one of four logic signals, used in the CLB.
•
•
Since the function-generator outputs are brought out inde-
pendently of the flip-flop outputs, and DIN and H1 can be
used as direct inputs to the two flip-flops, the two combina-
torial and the two sequential functions in the CLB can be
used independently. This versatility increases logic den-
sity and simplifies routing.
The asynchronous flip-flop input can be configured as
either set or reset. This configuration option also deter-
mines the state in which the flip-flops become operational
after configuration, as well as the effect of an externally or
internally applied Set/Reset during normal operation.
Fast Carry Logic
The CLBs can generate the arithmetic-carry output for
incoming operands, and can pass this extra output on to
the next CLB function generator above or below. This
connection is independent of normal routing resources
and it is, presently, only supported by Hard Macros. A later
software release will accommodate Soft Macros and will
permit graphic editing of the fast logic circuitry. This fast
carry logic is one of the most significant improvements in
the XC4000 families, speeding up arithmetic and counting
into the 60-MHz range.
Using Function Generators as RAMs
Using XC4000 devices, the designer can write into the
latches that hold the configuration content of the function
generators. Each function generator can thus be used as
a small Read/Write memory, or RAM. The function gen-
erators in any CLB can be configured in three ways.
•
•
•
Enable Clock, Asynchronous Preset/Reset, DIN, and
H1, when the memory function is disabled, or
Enable Clock, Write Enable, D0, and D1, when the
memory function is enabled.
Two 16 x 1 RAMs with two data inputs and two data
outputs – identical or, if preferred, different address-
ing for each RAM
One 32 x 1 RAM with one data input and one data
output
One 16 x 1 RAM plus one 5-input function generator