XC4005-5PC84C Xilinx Inc, XC4005-5PC84C Datasheet - Page 26

• Manufacturer Part Number: XC4005-5PC84C
• Description: IC LOGIC CL ARRAY 5000GAT 84PLC
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005-5PC84C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 61
• Number Of Gates: 5000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1068

XC4000, XC4000A, XC4000H Logic Cell Array Families
Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device ) on its DOUT
pin. There is an internal pipeline delay of 1.5 CCLK
periods, which means that DOUT changes on the falling
CCLK edge, and the next LCA device in the daisy-chain
accepts data on the subsequent rising CCLK edge. The
user can specify Fast ConfigRate, which starting some-
where in the first frame, increases the CCLK frequency
eight times, from a value between 0.5 and 1.25 MHz, to a
value between 4 and 10 MHz. Note that most Serial
PROMs are not compatible with this high frequency.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
GENERAL-
PURPOSE
USER I/O
PROGRAM
PINS
• •
• •
•
DOUT
HDC
LDC
INIT
PROGRAM
M0 M1
OTHER
I/O PINS
XC4000
(A LOW LEVEL RESETS THE XC17xx ADDRESS POINTER)
M2
DONE
CCLK
INIT
DIN
2-32
TO INIT PINS OF OPTIONAL SLAVE
XC4000 OR XC3000 DEVICES SHARING
THE CONFIGURATION BITSTREAM
TO DIN OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH DIFFERENT
CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH DIFFERENT
CONFIGURATIONS
DATA
CLK
CE
OE/RESET
restricted to be a permanently High user output. Using
DONE can also avoid contention on DIN, provided the
early DONE option is invoked.
How to Delay Configuration After Power-Up
There are two methods to delay configuration after power-
up: Put a logic Low on the PROGRAM input, or pull the
bidirectional INIT pin Low, using an open-collector (open-
drain) driver. (See also Figure 20 on page 2-27.)
A Low on the PROGRAM input is the more radical ap-
proach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the XC4000 device keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the begin-
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration, causes the LCA
device to wait after having completed the configuration
memory clear operation. When INIT is no longer held Low
+5 V
V
TO CCLK OF OPTIONAL
SLAVE LCA DEVICES WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCA DEVICES WITH IDENTICAL
CONFIGURATIONS
CC
XC17xx
MEMORY
SERIAL
V
PP
CEO
CE
OE/RESET
DATA
CLK
CASCADED
MEMORY
SERIAL
X6077