20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 346

• Manufacturer Part Number: 20-668-0024
• Description: IC CPU RABBIT4000 128-LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0024

• Processor Type: Rabbit 4000 8-bit
• Speed: 60MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 20-668-0022; 316-1078

4. DMA/block copy interaction — when a DMA transfer occurs during a block copy
5. Single-byte timed and external DMA requests to internal I/O registers — when
6. Wait states when moving from advanced 16-bit mode to basic modes — a wait state
336
instruction (LDIR, LDDR, COPY, COPYR, UMA, or UMS) while executing code out
of 16-bit memory with the “advanced 16-bit mode” enabled, the code prefetch queue
and program counter will become out-of-synch. This means that one or two incorrect
bytes (depending on the 16-bit alignment of the instruction) are reloaded and presented
to the processor as instructions when execution is “rewound” after the DMA transfer.
The result of this mismatch is that the block copy instruction does not complete.
The only way to prevent this from occurring is to prevent DMA transfers during block
copy instructions, either by disabling the DMA or by increasing the processor priority
above the priority of the DMA transfer.
There is a workaround. The processor’s BC register is used as a program counter by the
block copy instructions, and will be nonzero if the block copy instruction did not com-
plete. By checking the value of BC and jumping back to the block copy instruction if it
is nonzero, the block copy instruction is restarted with all the current register values
(source and destination pointers) and will continue where it left off. Rabbit Semicon-
ductor’s Dynamic C compiler automatically includes this wrapper code whenever it
identifies a block copy instruction.
timed or external DMA requests are enabled and set to transfer a single byte at a time to
an internal I/O register, two bytes will actually be transferred.
The simplest workaround is to double each data byte in the buffer; two bytes will be
transmitted, but they will be identical, so the actual I/O register setting will not change.
may be missed when certain instructions transfer execution from a device operating in
the advanced 16-bit mode to a device operating in a different memory interface mode.
Depending on the characteristics of the memory being accessed, this can lead to a
missed or incorrect instruction byte being read.
The exact circumstances that cause the missed wait state are complicated to predict be-
cause they involve the advanced 16-bit operating mode. In this mode a semi-autonomous
prefetch mechanism fetches words from a 16-bit memory to feed to the instruction
decoder. The fetched instruction bytes are presented to the instruction decoder on an as-
needed basis, which is only loosely coupled to the operation of the external memory bus.
The bug can only occur if the following conditions are met.
Whether the bug occurs is a function of when the instruction decoder accepts the JP
instruction relative to the fetch of the next instruction on the bus. This in turn depends
on both the instructions immediately prior to the JP instruction and the number of wait
states used by the prefetch mechanism.
1. One of these three instructions is used — JP (HL), JP (IX), or JP (IY).
2. The jump is from a memory using the advanced 16-bit mode into a memory that is not using the
3. The destination memory requires wait states.
advanced 16-bit mode.
Rabbit 4000 Microprocessor User’s Manual