20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 353

• Manufacturer Part Number: 20-668-0024
• Description: IC CPU RABBIT4000 128-LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 20-668-0024

• Processor Type: Rabbit 4000 8-bit
• Speed: 60MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 20-668-0022; 316-1078

registers
Index
alphabetic listing (continued)
PWMxR ...................... 245
PWUER ....................... 296
QDCR ......................... 237
QDCSR ....................... 236
QDCxHR ..................... 237
QDCxR ....................... 237
QDUER ....................... 296
RAMSR ......................... 58
RTCCR ......................... 37
RTCxR .......................... 37
RTUER ....................... 294
SAUER ....................... 298
SBUER ........................ 298
SCUER ........................ 298
SDUER ....................... 298
SEGSIZ ......................... 55
SEUER ........................ 298
SFUER ........................ 299
SPCR . 29, 75, 80, 171, 256
SPDxR ......................... 170
SPSR ........................... 170
SPUER ........................ 294
STKCR .......................... 62
STKHLR ....................... 63
STKLLR ....................... 62
STKSEG ....................... 53
STKSEGH ..................... 54
STKSEGL ..................... 54
SWDTR ......................... 38
SxAR ................... 138, 155
SxCR ........................... 158
SxCr ............................ 141
SxDHR ................ 144, 160
SxDLR ................ 143, 160
SxDR ................... 138, 155
SxER (asynch mode)
SxER (clocked serial mode)
SxER (HDLC mode) ... 160
SxLR ................... 138, 155
SxSR (asynch mode)
SxSR (clocked serial mode)
SxSR (HDLC mode) ... 157
TACR .......................... 113
TACSR ........................ 112
TAPR .......................... 112
TATxR ........................ 113
TAUER ....................... 297
TBCLR ........................ 120
........................... 142, 159
................................... 143
........................... 139, 156
................................... 140
registers
alphabetic listing (continued)
bootstrap ............................ 26
breakpoints ...................... 265
clocks ................................ 10
TBCMR ....................... 119
TBCR .......................... 118
TBCSR ........................ 118
TBLxR ........................ 119
TBMxR ....................... 119
TBSLxR ...................... 119
TBSMxR ..................... 119
TBUER ....................... 297
TCBAR ....................... 127
TCBPR ........................ 128
TCCR .......................... 126
TCCSR ........................ 126
TCDHR ....................... 126
TCDLR ....................... 126
TCRxHR ..................... 127
TCRxLR ...................... 127
TCSxHR ...................... 127
TCSxLR ...................... 127
TCUER ....................... 297
VRAM00–VRAM1F .... 40
WDTCR ........................ 37
WDTTR ........................ 38
WPCR ........................... 59
WPSxHR ....................... 62
WPSxLR ....................... 61
WPSxR .......................... 61
WPxR ............................ 60
Breakpoint x Address 0
Breakpoint x Address 1
Breakpoint x Address 2
Breakpoint x Control
Breakpoint x Mask 0
Breakpoint x Mask 1
Breakpoint x Mask 2
Breakpoint/Debug Control
Global Clock Double
Global Clock Modulator 0
Global Clock Modulator 1
Register .................... 269
Register .................... 269
Register .................... 269
Register .................... 268
Register .................... 270
Register .................... 270
Register .................... 270
Register .................... 268
Register ...................... 22
Register ...................... 21
Register ...................... 21
registers
clocks (continued)
DMA channels ................ 176
Global Control/Status
Global Output Control
Network Port A Control
DMA Master Auto-Load
DMA Master Control
DMA Master Control/Status
DMA Master Halt Register
DMA Master Request 0
DMA Master Request 1
DMA Master Timing
DMA Source Addr[7:0]
DMA Timed Request
DMA Timed Request Di-
DMA Timed Request Di-
DMA x Buffer Complete
DMA x Buffer Unused[15:8]
DMA x Buffer Unused[7:0]
DMA x Control Register 196
DMA x Destination
DMA x Destination
DMA x Destination
DMA x Initial Addr[15:8]
DMA x Initial Addr[23:16]
DMA x Initial Addr[7:0]
DMA x Length[15:8]
DMA x Length[7:0]
Register ...................... 20
Register ...................... 23
Register ...................... 24
Register .................... 187
Register .................... 188
Register .................... 187
Control Register ....... 190
Control Register ....... 191
Control Register ....... 189
Register .................... 198
Control Register ....... 192
vider High Register .. 192
vider Low Register ... 192
Register .................... 188
Register .................... 194
Register .................... 193
Addr[15:8] Register . 199
Addr[23:16] Register 199
Addr[7:0] Register ... 199
Register .................... 194
Register .................... 194
Register .................... 194
Register .................... 197
Register .................... 197
................................... 187
343