MPC870CVR133 Freescale Semiconductor, MPC870CVR133 Datasheet - Page 66

• Manufacturer Part Number: MPC870CVR133
• Description: IC MPU POWERQUICC 133MHZ 256PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICCr

Specifications of MPC870CVR133

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 133 MHz
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• I/o Voltage: 5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 8 KB
• Program Memory Type: EPROM/Flash
• Core Size: 32 Bit
• Cpu Speed: 133MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 256
• Supply Voltage Range: 1.7V To 1.9V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CPM Electrical Characteristics
1
Table 29
1
Figure 64
66
Num
Num
210
211
SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) × pre_scalar × 2).
The ratio SYNCCLK/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.
200
200
202
203
204
205
206
207
208
209
210
211
SCL frequency is given by SCL = BRGCLK_frequency/((BRG register + 3) × pre_scalar × 2).
The ratio SYNCCLK/(BRGCLK/pre_scalar) must be greater than or equal to 4/1.
SDA
SCL
SDL/SCL fall time
Stop condition setup time
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
provides the I
shows the I
205
202
2
C bus timing.
2
206
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
C (SCL > 100 kHz) timings.
Characteristic
Table 28. I
203
1
Table 29. I
Figure 64. I
Characteristic
2
C Timing (SCL < 100 kH
2
207
C Timing (SCL > 100 kH
2
209
C Bus Timing Diagram
204
Expression
fSCL
fSCL
210
—
—
—
—
—
—
—
—
—
—
Z
) (continued)
BRGCLK/16512
Z
1/2(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(40 × fSCL)
)
Min
—
—
0
0
All Frequencies
208
All Frequencies
Min
4.7
—
Freescale Semiconductor
1/(10 × fSCL)
1/(33 × fSCL)
211
BRGCLK/48
BRGCLK/48
Max
—
—
—
—
—
—
—
—
Max
300
—
Unit
Unit
Hz
Hz
ns
μs
s
s
s
s
s
s
s
s
s
s