MPC870CVR133 Freescale Semiconductor, MPC870CVR133 Datasheet - Page 68
MPC870CVR133
Manufacturer Part Number
MPC870CVR133
Description
IC MPU POWERQUICC 133MHZ 256PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICCr
Datasheet
1.MPC870VR80.pdf
(84 pages)
Specifications of MPC870CVR133
Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
133MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
256-PBGA
Processor Series
MPC8xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
133 MHz
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Data Ram Size
8 KB
I/o Voltage
5 V
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
Program Memory Size
8 KB
Program Memory Type
EPROM/Flash
Core Size
32 Bit
Cpu Speed
133MHz
Digital Ic Case Style
BGA
No. Of Pins
256
Supply Voltage Range
1.7V To 1.9V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC870CVR133
Manufacturer:
Freescale
Quantity:
560
Company:
Part Number:
MPC870CVR133
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
FEC Electrical Characteristics
Figure 65
15.2
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1%.
Table 32
68
M20_RMII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup
M21_RMII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising
Num
M5
M6
M7
M8
provides information on the MII transmit signal timing.
MII_RXD[3:0] (Inputs)
MII and Reduced MII Transmit Signal Timing
shows MII receive signal timing.
MII_RX_CLK (Input)
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
MII_TX_CLK pulse width low
edge
MII_RX_DV
MII_RX_ER
MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4
Figure 65. MII Receive Signal Timing Diagram
Characteristic
Table 32. MII Transmit Signal Timing
M1
M2
M3
M4
35%
35%
Min
—
5
4
2
Max
65%
65%
25
—
—
—
Freescale Semiconductor
MII_TX_CLK period
MII_TX_CLK period
Unit
ns
ns
ns
ns