Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 116
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
Write Register 2 Group
Write Register 3 Group
Bits 7, 2, 1, and 0, depicted in Figure 42, specify the base register byte for
this group. The group is used only when Port B is used, for example, do not
program it for a search-only, simultaneous transfer, or simultaneous
transfer/search with Port A as the source. Its syntax is the same as WR1.
Figure 42.
Bits 7, 1, and 0, depicted in Figure 43, specify the base register byte for this
group. The group is used primarily to specify the stop-on-match condition
as well as the specific match byte for a search operation. It can perform fast,
one-byte enabling of both bus requests and interrupts. A description of its
functions follows.
WR Ends 1/2 Cycle Early = 0
RD Ends 1/2 Cycle Early = 0
MREQ Ends 1/2 Cycle Early = 0
Write Register 2 Group
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
1
1
0
1
0
1
= Port B Address Decrements
= Port B Address Increments
= Port B Address Fixed
0 = Port B is Memory
0 = Port B is I/O
0
0 = IORQ Ends 1/2 Cycle Early
0
0
1
1
0
0
1
0
1
0
= Cycle Length = 4
= Cycle Length = 3
= Cycle Length = 2
= Do Not Use
Port B Variable
Timing Byte
Base Register Byte
Direct Memory Access
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