Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 312
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Read Registers
The Z80 SIO contains three registers, RR2-RR0 (Figure 122 through
Figure 124), that are read to obtain the status information for each channel,
with the exception of RR2-Channel B. The status information includes error
conditions, interrupt vector, and standard communications-interface signals.
To read the contents of a selected read register other than RRD, the system
program must first write the pointer byte to WR0, in exactly the same way
as a write register operation. Then, by executing an input instruction, the
contents of the addressed read register can be read by the CPU.
The status bits of RR0 and RR1 are carefully grouped to simplify status
monitoring. For example, when the interrupt vector indicates that a Special
Receive Condition interrupt occurred, all the appropriate error bits can be
read from a single register (RR1).
Read Register 0
This register contains the status of the receive and transmit buffers; the
DCD, CTS, and SYNC inputs; the Transmit Underrun/EOM latch; and the
Break/Abort latch.
Table 31. Read Register 0 Rx and Tx Buffers
Receive Character Available (DO)
This bit is set when at least one character is available in the receive buffer;
it is reset when the receive FIFO is empty.
Break/
Abort
D7
Underrun
Transmit
EOM
D6
CTS
IDS
Empty
Buffer
Sync/
Hunt
D4
DCD
D3
Transmit
Pending
D2
Serial Input/Output
Interrupt
Pending
(Ch.A
only)
D1
Character
available
Receive
D0
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