Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 47
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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7 U G T / C P W C N
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T
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1
2
W
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3
4
1
CLK
M1
IORQ
RD
IEI
INT
DATA
Vector
Figure 12.
Interrupt Acknowledge Cycle
Return from Interrupt Cycle
Figure 13 illustrates the timing associated with the RETI Instruction. This
instruction is used at the end of an Interrupt Service Routine to initialize
the daisy-chain enable lines for control of nested priority interrupt
handling. The CTC decodes the two-byte RETI code internally and
determines whether it is intended for a channel being serviced.
When several Z80 peripheral chips are in the daisy-chain, IEI becomes
active on the chip currently under service when an EDH Op Code is
decoded. If the following Op Code is
, the peripheral being serviced is
4DH
re-initialized and its IEO becomes active.
UM008101-0601
Counter/Timer Channels
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