Z0847006PSG Zilog, Z0847006PSG Datasheet - Page 44
Z0847006PSG
Manufacturer Part Number
Z0847006PSG
Description
IC 6MHZ Z80 NMOS DART 40-DIP
Manufacturer
Zilog
Series
Z80r
Datasheet
1.Z0847006PSG.pdf
(330 pages)
Specifications of Z0847006PSG
Processor Type
Z80
Features
Dual Channel Asynchronous Receiver/Transmitter (DART)
Speed
6MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Mounting Style
Through Hole
Cpu Speed
6MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
847006
Rohs Compliant
Yes
Clock Frequency
6MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z0847006PSG
Manufacturer:
Zilog
Quantity:
22
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UM008101-0601
< % 2 7 2 G T K R J G T C N U
7 U G T / C P W C N
CTC Counting and Timing
CS0. CS1, CE
Figure 10.
Figure 11 illustrates the timing diagram for the CTC Counting and Timing
modes.
In the Counter mode, the edge (rising edge is active in this example) from
the external hardware connected to pin CLK/TRG, decrements the down-
counter in synchronization with the System Clock Φ. This CLK/TRG pulse
must have a minimum width and the minimum period must not be less than
twice the System clock period. Although there is no setup time requirement
between the active edge of the CLK/TRG and the rising edge of Φ, if the
CLK/TRG edge occurs closer than a specified minimum time, the
decrement of the down-counter will be delayed one cycle of Φ.
Immediately after the 1 to 0 decrement of the down-counter, the ZC/TO
output is pulsed true.
In the Timer mode, a pulse trigger (user selectable as either active High or
active Low) at the CLK/TRG pin enables the timing function on the second
succeeding rising edge of Φ. As in the Counter mode, the triggering pulse is
DATA
IORQ
CLK
RD
M1
CTC Read Cycle
T
1
T
2
Channel Address
T
WA
OUT
T
3
Counter/Timer Channels
T
1
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